1. Field of the Invention
This invention relates generally to semiconductor fabrication technology, and, more particularly, to a method of using scatterometry measurements to control stepper process parameters, and a system for accomplishing same.
2. Description of the Related Art
There is a constant drive within the semiconductor industry to increase the operating speed of integrated circuit devices, e.g., microprocessors, memory devices, and the like. This drive is fueled by consumer demands for computers and electronic devices that operate at increasingly greater speeds. This demand for increased speed has resulted in a continual reduction in the size of semiconductor devices, e.g., transistors. That is, many components of a typical field effect transistor (FET), e.g., channel length, junction depths, gate insulation thickness, and the like, are reduced. For example, all other things being equal the smaller the channel length of the transistor, the faster the transistor will operate. Thus, there is a constant drive to reduce the size, or scale, of the components of a typical transistor to increase the overall speed of the transistor, as well as integrated circuit devices incorporating such transistors.
By way of background, an illustrative field effect transistor 10, as shown in FIG. 1, may be formed above a surface 15 of a semiconducting substrate or wafer 11 comprised of doped-silicon. The substrate 11 may be doped with either N-type or P-type dopant materials. The transistor 10 may have a doped polycrystalline silicon (polysilicon) gate electrode 14 formed above a gate insulation layer 16. The gate electrode 14 and the gate insulation layer 16 may be separated from doped source/drain regions 22 of the transistor 10 by a dielectric sidewall spacer 20. The source/drain regions 22 for the transistor 10 may be formed by performing one or more ion implantation processes to introduce dopant atoms, e.g., arsenic or phosphorous for NMOS devices, boron for PMOS devices, into the substrate 11. Shallow trench isolation regions 18 may be provided to isolate the transistor 10 electrically from neighboring semiconductor devices, such as other transistors (not shown).
The gate electrode 14 has a critical dimension 12, ie., the width of the gate electrode 14, that approximately corresponds to the channel length 13 of the device when the transistor 10 is operational. Of course, the critical dimension 12 of the gate electrode 14 is but one example of a feature that must be formed very accurately in modem semiconductor manufacturing operations. Other examples include, but are not limited to, conductive lines, openings in insulating layers to allow subsequent formation of a conductive interconnection, i.e., a conductive line or contact, therein, etc.
In the process of forming integrated circuit devices, millions of transistors, such as the illustrative transistor 10 depicted in FIG. 1, are formed above a semiconducting substrate. In general, semiconductor manufacturing operations involve, among other things, the formation of layers of various materials, e.g., polysilicon, insulating materials, etc., and the selective removal of portions of those layers by performing known photolithographic and etching techniques. These processes are continued until such time as the integrated circuit device is complete. Additionally, although not depicted in FIG. 1, a typical integrated circuit device is comprised of a plurality of conductive interconnections, such as conductive lines and conductive contacts or vias, positioned in multiple layers of insulating material formed above the substrate. These conductive interconnections allow electrical signals to propagate between the transistors formed above the substrate.
During the course of fabricating such integrated circuit devices, a variety of features, e.g., gate electrodes, conductive lines, openings in layers of insulating material, etc., are formed to very precisely controlled dimensions. Such dimensions are sometimes referred to as the critical dimension (CD) of the feature. It is very important in modern semiconductor processing that features be formed as accurately as possible due to the reduced size of those features in such modern devices. For example, gate electrodes may now be patterned to a width 12 that is approximately 0.2 xcexcm (2000 xc3x85), and further reductions are planned in the future. As stated previously, the width 12 of the gate electrode 14 corresponds approximately to the channel length 13 of the transistor 10 when it is operational. Thus, even slight variations in the actual dimension of the feature as fabricated may adversely affect device performance. Thus, there is a great desire for a method that may be used to accurately, reliably and repeatedly form features to their desired critical dimension, i.e., to form the gate electrode 14 to its desired critical dimension 12.
Photolithography is a process typically employed in semiconductor manufacturing. Photolithography generally involves forming a patterned layer of photoresist above one or more layers of material that are desired to be patterned, and using the patterned photoresist layer as a mask in subsequent etching processes. In general, in photolithography operations, the pattern desired to be formed in the underlying layer or layers of material is initially formed on a reticle. Thereafter, using an appropriate stepper tool and known photolithographic techniques, the image on the reticle is transferred to the layer of photoresist. Then, the layer of photoresist is developed so as to leave in place a patterned layer of photoresist substantially corresponding to the pattern on the reticle. This patterned layer of photoresist is then used as a mask in subsequent etching processes, wet or dry, performed on the underlying layer or layers of material, e.g., a layer of polysilicon, metal or insulating material, to transfer the desired pattern to the underlying layer. The patterned layer of photoresist is comprised of a plurality of features, e.g., line-type features or opening-type features, that are to be replicated in an underlying process layer. The features in the patterned layer of photoresist also have a critical dimension, sometimes referred to as a develop inspect critical dimension (DICD).
FIGS. 2 and 3 depict an illustrative embodiment of a wafer 11 that may be subjected to an exposure process in a stepper tool. In general, the stepper exposure process is performed on a stack comprised of one or more process layers or films and a layer of photoresist. For example, as shown in FIG. 2, such a stack may be comprised of a layer of polysilicon 36, formed above the substrate 11, and a layer of photoresist 38. Alternatively, an anti-reflective coating (ARC) layer (not shown) may be positioned above the layer of polysilicon 36 and below the layer of photoresist 38. Of course, such film stacks may be comprised of a vast variety of combinations of process layers and materials.
As shown in FIG. 3, a plurality of die 42 are formed above the wafer 11. The die 42 define the area of the wafer 11 where production integrated circuit devices, e.g., microprocessors, ASIC, memory devices, will be formed. The size, shape and number of die 42 per wafer 11 depend upon the type of device under construction. For example, several hundred die 42 may be formed above an 8-inch diameter wafer 11. The wafer 11 may also have an alignment notch 17 that is used to provide relatively rough alignment of the wafer 11 prior to performing certain processes, e.g., an exposure process in a stepper tool.
As shown in FIG. 2, the stepper tool contains a representative light source 47 that is used to project light through a reticle (not shown) onto a layer of photoresist 38. Ultimately, the image in the reticle will be transferred to the layer of photoresist 38, and the underlying process layer 36 will be patterned using the patterned layer of photoresist 38 as a mask during one or more subsequent etching processes.
The exposure process performed on the wafer 11 is typically performed on a flash-by-flash basis as the wafer 11 is moved, or stepped, relative to the light source 47. During each step, the light source 47 projects light onto a given area of the wafer 11, i.e., each flash is projected onto an exposure field 41. The size of the exposure field 41, as well as the number of die 42 within each exposure field 41, may vary greatly. For example, an illustrative exposure field 41 is depicted in FIG. 3 wherein four of the die 42 fall within the exposure field 41, i.e., a so-called 2xc3x972 pattern. However, the number of die 42 and size of the exposure field 41 may vary. For example, integrated circuits may be exposed using a 1xc3x972 pattern (covering 2 die), a 5xc3x975 pattern (covering 25 die), etc. The precise pattern of the exposure field 41 may be based upon the product under construction as well as the desires and judgment of the appropriate process engineer.
One parameter of the stepper exposure process that is of critical importance is the location of the focal plane of the stepper. In general, the focal plane of the stepper is the point where the image plane and the object plane coincide. The location of the focal plane may vary based upon a variety of factors, e.g., the type of photoresist material used, the composition of the underlying process layers, the thickness of the layer of photoresist, etc. Ideally, the focal plane will be located at a position that produces acceptable DICD dimensions and profiles in the layer of photoresist 38. In the illustrative example depicted in FIG. 2, the focal plane of the stepper tool is located at the approximate middle of the layer of photoresist 38, as indicated by the lines 39. The focal plane may be located at the line 39 within the layer of photoresist 38, as indicated in FIG. 2, or it may be located at another point, i.e., at the surface 43 of the layer of photoresist 38. The location of the focal plane may vary greatly based upon a number of features, such as the type and thickness of the layer of photoresist 38, as well as the composition and thickness of the underlying process layers.
Due to a variety of reasons, the thickness of the layer of photoresist 38, as well as the position of its surface 43 relative to the light source 47, may vary across the wafer 11 and among the various exposure fields 41. As a result, the ideal location of the focal plane for the stepper exposure process may vary among the exposure fields 41. For example, the layer of photoresist 38 within a particular exposure field 41 may be thinner than anticipated. As a result, the focal plane of the stepper may be positioned above the ideal location, thereby producing features in the layer of photoresist 38 in that exposure field 41 with rounded corners of a magnitude that are unacceptable. In turn, this may result in distortion of the features in the underlying process layer 36.
Normally, it is desirable that the surface 43 of the layer of photoresist 38 will be positioned approximately perpendicular to the incident light from the light source 47 during the exposure process. This is desired to reduce the magnitude of diffracted light from the light source. However, for a variety of reasons, the surface 43 of the layer of photoresist 38 may be tilted in one or more directions as indicated by the dashed line 43A and the angle 44. Accordingly, most modem stepper tools are provided with means for compensating for the tilt in the layer of photoresist 38, e.g., by adjusting the tilt of the reticle (not shown) and/or the tilt of the wafer 11, such that the approximately perpendicular relationship is maintained between the tilted surface 43 of the layer of photoresist 38 and the light from the light source 47. Variations in the tilt of the surface 43 of the layer of photoresist 38 may occur for a number of reasons, e.g., underlying topography, excessive spinning during the process of forming the layer of photoresist 38, variations in the temperature of the photoresist, variations in cool plate or oven temperatures, etc. Moreover, such tilt variations may be different in different exposure fields 41 of the wafer 11.
Variations that may occur during stepper exposure processes, such as variations in the location of the focal plane and the tilt of the surface 43 of the layer of photoresist 38, may result in the features formed in the patterned layer of photoresist 38 having undesirable characteristics. For example, if a layer of photoresist 38 is exposed with the focal plane located above the desired location of the focal plane, the features formed in the patterned layer of photoresist 38 will have rounded corners on top of the photoresist. As a result, features formed in the underlying process layer will exhibit similar characteristics. On the other hand, if the layer of photoresist 38 is exposed using a focal plane that is located below the desired location of the focal plane, the features in the underlying process layer 36 will tend to exhibit undercutting. Performing the exposure process in exposure fields 41 wherein the surface 43 of the layer of photoresist 38 is not substantially perpendicular to the light generated by the stepper tool, results in similar problems.
In turn, such problems may lead to excessive rework of the patterned layer of photoresist 38, ie., the incorrectly formed layer of photoresist 38 may have to be removed, and the process may have to be repeated. Even worse, if undetected, the variations in the patterned layer of photoresist 38 resulting from variations in the tilt angle and/or location of the focal plane of the exposure process may ultimately lead to the formation of features, e.g., gate electrodes, having dimensions that are not acceptable for the particular integrated circuit device under construction. For example, transistors may be produced with gate electrodes that are too wide (relative to a preestablished target value), thereby producing transistor devices that operate at less than desirable switching speeds. All of these problems result in delays, waste, excessive costs and cause reduced yields of the manufacturing operations.
The present invention is directed to a method and system that may solve, or at least reduce, some or all of the aforementioned problems.
The present invention is generally directed to a method of using scatterometry measurements to control stepper process parameters. In one illustrative embodiment, the method comprises providing a library of optical characteristic traces, each of which corresponds to a grating structure comprised of a plurality of features having a known profile, forming a plurality of grating structures in a layer of photoresist, each of the formed grating structures being comprised of a plurality of features having an unknown profile, and illuminating the formed grating structures. The method further comprises measuring light reflected off of each of the plurality of formed grating structures to generate an optical characteristic trace for each of the formed grating structures, comparing each of the generated optical characteristic traces to at least one optical characteristic trace from the library, and modifying at least one parameter of a stepper exposure process to be performed on at least one subsequently processed wafer based upon the comparison of the generated optical characteristic traces and the at least one optical characteristic trace from the library.
In another illustrative embodiment, the method comprises providing a wafer having at least one process layer and a layer of photoresist formed thereabove, forming a plurality of grating structures in the layer of photoresist, illuminating the grating structures, and measuring light reflected off of the grating structures to generate an optical characteristic trace for each of the grating structures. The method further comprises comparing the generated optical characteristic traces to a target optical characteristic trace, and determining, based upon a comparison of the generated optical characteristic traces and the target optical characteristic trace, at least one parameter of an exposure process to be performed on a layer of photoresist formed on a subsequently processed wafer. In other embodiments of the invention, at least three, at least five, or at least nine of the grating structures are formed in a layer of photoresist. In yet another embodiment, the invention comprises modifying at least one parameter of a stepper exposure process to be performed on a subsequently processed wafer based upon a deviation between the generated optical characteristic trace and the target optical characteristic trace.